View MAX9218ECMVTGB_8801468.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max9218 digital video serial-to-parallel converterdeserializes a total of 27 bits during data and control phases. in the data phase, the lvds serial input is con- verted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. the separate video and control phases take advantage of video timing to reduce the serial data rate. the max9218 pairs with the max9217 serializer to form a complete digital video transmission system. proprietary data decoding reduces emi and provides dc balance. the dc balance allows ac-coupling, pro- viding isolation between the transmitting and receiving ends of the interface. the max9218 features a selec- table rising or falling output latch edge. esd tolerance is specified for iso 10605 with ?0kv contact discharge and ?0kv air discharge. the max9218 operates from a +3.3v core supply and features a separate output supply for interfacing to 1.8v to 3.3v logic-level inputs. this device is available in 48- lead thin qfn and lqfp packages and is specified from -40? to +85?. applications navigation system displayin-vehicle entertainment system video camera lcd displays features ? proprietary data decoding for dc balance andreduced emi ? control data deserialized during video blanking ? five control data inputs are single bit-errortolerant ? output transition time is scaled to operatingfrequency for reduced emi ? staggered output switching reduces emi ? output enable allows busing of outputs ? clock pulse stretch on lock ? wide ?% reference clock tolerance ? synchronizes to max9217 serializer withoutexternal control ? iso 10605 esd protection ? separate output supply allows interface to 1.8vto 3.3v logic ? +3.3v core power supply ? space-saving thin qfn and lqfp packages ? -40? to +85? operating temperature max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer ________________________________________________________________ maxim integrated products 1 de_outcntl_out8 cntl_out7 cntl_out6 cntl_out5 cntl_out4 cntl_out3 cntl_out2 cntl_out1t cntl_out0 outen pwrdwn v cco gnd v cco rgb_out8rgb_out9 rgb_out10rgb_out11 rgb_out12 rgb_out13 rgb_out14 rgb_out15 rgb_out16 rgb_out17 3738 39 40 41 42 43 44 45 46 47 48 2423 22 21 20 19 18 17 16 15 14 13 lqfp + max9218 3635 34 33 32 31 30 29 28 27 26 25 rgb_out7rgb_out6 rgb_out5 rgb_out4 rgb_out3 rgb_out2 rgb_out1 rgb_out0 pclk_out lock v cco v cco gnd r/f rng1 v cclvds in+ in- lvds gnd pll gnd v ccpll rng0 gnd v cc refclk rgb_out7 rgb_out6rgb_out4 rgb_out3 rgb_out0 pclk_out lockv cco gnd v cco rgb_out2rgb_out1 rgb_out5 top view v cclvds in+ in- lvds gnd pll gnd v ccpll rng0 refclk gnd v cc rng1 r/f + de_out cntl_out8cntl_out6 cntl_out5 cntl_out2 cntl_out1 cntl_out0 pwrdwn outen cntl_out4cntl_out3 cntl_out7 rgb_out8 rgb_out9 rgb_out10 rgb_out11 rgb_out12 rgb_out13 rgb_out14rgb_out17 rgb_out15 v cco v cco gnd 3738 39 40 41 42 43 44 45 46 47 48 2423 22 21 20 19 18 17 16 15 14 13 thin qfn-ep max9218 3635 34 33 32 31 30 29 28 27 26 25 12 3 4 5 6 7 8 9 1011 12 12 3 4 5 6 7 8 9 1011 12 rgb_out16 part temp range pin-package max9218ecm+ -40 c to +85 c 48 lqfp max9218ecm/v+ -40 c to +85 c 48 lqfp max9218etm+ -40 c to +85 c 48 thin qfn-ep* pin configurations ordering information 19-3557; rev 5; 8/09 + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. * ep = exposed pad. evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim's website at www.maxim-ic.com. downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(v cc_ = +3.0v to +3.6v, pwrdwn = high, differential input voltage ? v id ? = 0.05v to 1.2v, input common-mode voltage v cm = ? v id /2 ? to v cc - ? v id /2 ? , t a = -40? to +85?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc_ to _gnd........................................................-0.5v to +4.0v any ground to any ground...................................-0.5v to +0.5v in+, in- to lvds gnd...........................................-0.5v to +4.0v in+, in- short circuit to lvds gnd or v cclvds ......continuous in+, in- short through 0.125? (or smaller), 25v series capacitor..........................................-0.5v to +16v (r/ f , outen, rng_, refclk, pwrdwn ) to gnd .................................-0.5v to (v cc + 0.5v) (rgb_out[17:0], cntl_out[8:0], de_out, pclk_out, lock ) to v cco gnd ...........................-0.5v to (v cco + 0.5v) continuous power dissipation (t a = +70?) 48-lead lqfp (derate 21.7mw/? above +70?) ....1739mw 48-lead thin qfn (derate 37mw/? above +70?) .2963mw esd protection machine model (r d = 0 , c s = 200pf) all pins to gnd ...........................................................?00v human body model (r d = 1.5k , c s = 100pf) all pins to gnd ..........................................................?.0kv iso 10605 (r d = 2k , c s = 330pf) contact discharge (in+, in-) to gnd............................?0kv air discharge (in+, in-) to gnd ....................................?0kv storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units single-ended inputs (r/ f , outen, rng0, rng1, refclk, pwrdwn ) high-level input voltage v ih 2.0 v cc + 0.3 v low-level input voltage v il -0.3 +0.8 v input current i in v in = -0.3v to (v cc + 0.3v), pwrdwn = high or low -70 +70 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (rgb_out[17:0], cntl_out[8:0], de_out, pclk_out, lock ) i oh = -100? v cco - 0.1 i oh = -2ma, rng1, rng0 = high v cco - 0.35 high-level output voltage v oh i oh = -2ma, rng1, rng0 both not high simultaneously v cco - 0.4 v i ol = 100? 0.1 i ol = 2ma, rng1, rng0 = high 0.3 low-level output voltage v ol i ol = 2ma, rng1, rng0 both not high simultaneously 0.35 v high-impedance output current i oz pwrdwn = low or outen = low, v o = -0.3v to v cco + 0.3v -10 +10 ? downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer _______________________________________________________________________________________ 3 dc electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, pwrdwn = high, differential input voltage ? v id ? = 0.05v to 1.2v, input common-mode voltage v cm = ? v id /2 ? to v cc - ? v id /2 ? , t a = -40? to +85?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units rng1, rng0 = high, v o = 0 -10 -50 output short-circuit current i os rng1, rng0 both not highsimultaneously, v o = 0 -7 -40 ma lvds input (in+, in-) differential input high threshold v th 50 mv differential input low threshold v tl -50 mv input current i in+ , i in- pwrdwn = high or low -20 +20 ? pwrdwn = high or low 35 50 65 k input bias resistor r ib v cc_ = 0 or open, pwrdwn = 0 or open, figure 1 35 50 65 k power-off input current i ino+ , i ino- v cc_ = 0 or open, pwrdwn = 0 or open -40 +40 ? power supply 3mhz 20 rng1 = low,rng0 = low 7mhz 35 7mhz 25 rng1 = high,rng0 = low 15mhz 47 15mhz 37 worst-case supply current i ccw c l = 8pf, worst-casepattern, figure 2 rng1 = high,rng0 = high 35mhz 70 ma power-down supply current i ccz (note 3) 50 ? downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 4 _______________________________________________________________________________________ note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to groundexcept v th and v tl . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are productiontested at t a = +25?. note 3: all lvttl/lvcmos inputs, except pwrdwn at 0.3v or v cc - 0.3v. pwrdwn is 0.3v. note 4: ac parameters are guaranteed by design and characterization, and are not production tested. limits are set at ? sigma. note 5: c l includes probe and test jig capacitance. ac electrical characteristics(v cc_ = +3.0v to 3.6v, c l = 8pf, pwrdwn = high, differential input voltage ? v id ? = 0.1v to 1.2v, input common-mode voltage v cm = ? v id /2 ? to v cc - ? v id /2 ? , t a = -40? to +85?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 4, 5) parameter symbol conditions min typ max units refclk timing requirements period t t 28.57 333.00 ns frequency f clk 3 35 mhz frequency variation ? f clk refclk to serializer pclk_in -2.0 +2.0 % duty cycle dc 40 50 60 % transition time t tran 20% to 80% 6 ns switching characteristics rng1, rng0 = high 3.2 4.4 output rise time t r figure 3 rng1, rng0 both not highsimultaneously 3.8 5.5 ns rng1, rng0 = high 2.7 4.5 output fall time t f figure 3 rng1, rng0 both not highsimultaneously 3.6 5.3 ns pclk_out high time t high figure 4 0.4 x t t 0.45 x t t 0.6 x t t ns pclk_out low time t low figure 4 0.4 x t t 0.45 x t t 0.6 x t t ns data valid before pclk_out t dvb figure 5 0.35 x t t 0.4 x t t ns data valid after pclk_out t dva figure 5 0.35 x t t 0.4 x t t ns input-to-output delay t delay figure 6 2.575 x t t + 8.5 2.725 x t t + 12.8 ns pll lock to refclk t pllref figure 7 16385 x t t ns power-down delay t pdd figure 7 100 ns output enable time t oe figure 8 30 ns output disable time t oz figure 9 30 ns downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer _______________________________________________________________________________________ 5 worst-case pattern supply current vs. frequency max9218 toc01 frequency (mhz) supply current (ma) 31 27 7 11 15 19 23 10 20 30 40 50 60 70 80 0 33 5 output transition time vs. output supply voltage (v cco ) max9218 toc02 output supply voltage (v) output transition time (ns) 3.0 2.7 2.4 2.1 1 2 3 4 5 6 70 1.8 3.3 rng1 = rng0 = high t r t f output transition time vs. output supply voltage (v cco ) max9218 toc03 output supply voltage (v) output transition time (ns) 3.0 2.7 2.4 2.1 1 2 3 4 5 6 70 1.8 3.3 rng1 = rng0 = both not high t r t f bit-error rate vs. cable length max9218 toc04 cat5e cable length (m) bit-error rate 16 12 8 4 10 -11 10 -12 10 -13 10 -14 10 -10 02 0 35mhz clock700mbps data rate for <12m, ber < 10 -12 cat5e typical operating characteristics (v cc _ = +3.3v, c l = 8pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 6 _______________________________________________________________________________________ pin description pin name function 1r / f rising or falling latch edge select. lvttl/lvcmos input. selects the edge of pclk_out forlatching data into the next chip. set r/ f = high for a rising latch edge. set r/ f = low for a falling latch edge. internally pulled down to gnd. 2 rng1 lvttl/lvcmos range select input. set to the range that includes the serializer parallel clock input frequency. internally pulled down to gnd. 3v cclvds lvds supply voltage. bypass to lvds gnd with 0.1? and 0.001? capacitors in parallel as closeto the device as possible, with the smallest value capacitor closest to the supply pin. 4 in+ noninverting lvds serial data input 5 in- inverting lvds serial data input 6 lvds gnd lvds supply ground 7 pll gnd pll supply ground 8v ccpll pll supply voltage. bypass to pll gnd with 0.1? and 0.001? capacitors in parallel as close tothe device as possible, with the smallest value capacitor closest to the supply pin. 9 rng0 lvttl/lvcmos range select input. set to the range that includes the serializer parallel clock input frequency. internal pulldown to gnd. 10 gnd digital supply ground 11 v cc digital supply voltage. supply for lvttl/lvcmos inputs and digital circuits. bypass to gnd with0.1? and 0.001? capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 12 refclk lvttl/lvcmos reference clock input. apply a reference clock that is within 2% of the serializer pclk_in frequency. internally pulled down to gnd. 13 pwrdwn lvttl/lvcmos power-down input. internally pulled down to gnd. 14 outen lvttl/lvcmos output enable input. high activates the single-ended outputs. driving low placesthe single-ended outputs in high impedance. internally pulled down to gnd. 15?3 cntl_out [8:0] lvttl/lvcmos control data outputs. cntl_out[8:0] are latched into the next chip on the rising or falling edge of pclk_out as selected by r/ f when de_out is low, and are held at the last state when de_out is high. 24 de_out lvttl/lvcmos data enable output. high indicates rgb_out[17:0] are active. low indicates cntl_out[8:0] are active. 25, 37 v cco gnd output supply ground 26, 38 v cco output supply voltage. bypass to gnd with 0.1? and 0.001? capacitors in parallel as close to thedevice as possible, with the smallest value capacitor closest to the supply pin. 27 lock lvttl/lvcmos lock indicator output. outputs are valid when lock is low. 28 pclk_out lvttl/lvcmos parallel clock output. latches data into the next chip on the edge selected by r/ f . 29?6, 39?8 rgb_out [17:0] lvttl/lvcmos red, green, and blue digital video data outputs. rgb_out[17:0] are latched intothe next chip on the edge of pclk_out selected by r/ f when de_out is high, and are held at the last state when de_out is low. ep exposed pad for thin qfn package only. connect to gnd. downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer _______________________________________________________________________________________ 7 functional diagram in+ in- rng0rng1 max9218 ser-to-par timing and control pll dc balance/ decode 1 0 r/fouten rgb_out[17:0] lock pwrdwn refclk pclk_out de_out cntl_out[8:0] lvdsreceiver 1.2v in+ r ib r ib in- figure 1. lvds input bias pclk_out odd rgb_out cntl_out even rgb_out cntl_out rising latch edge shown (r/f = high). figure 2. worst-case output pattern de_out lock pclk_out rgb_out[17:0] cntl_out[8:0] 0.9v cco 0.1v cco t f t r figure 3. output rise and fall times pclk_out t low t high 2.0v 0.8v figure 4. high and low times downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 8 _______________________________________________________________________________________ pclk_out pclk_out shown for r/f = high (rising latch edge) t dvb t dva 2.0v 2.0v 2.0v 0.8v 0.8v 0.8v de_out lock rgb_out[17:0] cntl_out[8:0] figure 5. synchronous output timing in+, in- pclk_out cntl_out rgb_out 20 serial bits pclk_out shown for r/f = high serial-word n serial-word n + 1 parallel-word n - 1 parallel-word n t delay figure 6. deserializer delay downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer _______________________________________________________________________________________ 9 pwrdwn refclk pclk_out rgb_out cntl_out de_out lock t pllref transition word found recovered clock clock stretch valid data high impedance high impedancehigh impedance high impedance high impedancehigh impedance note: r/f = high t pdd 0.8v 2.0v outen active high-z lock de_out rgb_out[17:0] cntl_out[8:0] t oe 0.8v figure 7. pll lock to refclk and power-down delay figure 8. output enable time outen high-z active lock de_out rgb_out[17:0] cntl_out[8:0] t oz 2.0v figure 9. output disable time downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 10 ______________________________________________________________________________________ detailed description the max9218 dc-balanced deserializer operates at aparallel clock frequency of 3mhz to 35mhz, deserializ- ing video data to the rgb_out[17:0] outputs when the data enable output de_out is high, or control data to the cntl_out[8:0] outputs when de_out is low. the video phase words are decoded using 2 overhead bits, en0 and en1. control phase words are decoded with 1 overhead bit, en0. encoding, performed by the max9217 serializer, reduces emi and maintains dc balance across the serial cable. the serial input word formats are shown in table 1 and table 2. control data inputs c0 to c4, each repeated over 3 seri- al bit times by the serializer, are decoded using majority voting. two or three bits at the same state determine the state of the recovered bit, providing single bit-error tol- erance for c0 to c4. the state of c5 to c8 is deter- mined by the level of the bit itself (no voting is used). ac-coupling benefits ac-coupling increases the input voltage of the lvdsreceiver to the voltage rating of the capacitor. two capacitors are sufficient for isolation, but four capaci- tors?wo at the serializer output and two at the deseri- alizer input?rovide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and common-mode noise. the max9217 serializer can also be dc-coupled to the max9218 deserializer. figure 10 is the ac-coupled serializer and deserializer with two capacitors per link, and figure 11 is the ac-coupled serializer and deseri- alizer with four capacitors per link. applications information selection of ac-coupling capacitors see figure 12 for calculating the capacitor values forac-coupling, depending on the parallel clock frequen- cy. the plot shows capacitor values for two- and four- capacitor-per-link systems. for applications using less than 18mhz clock frequency, use 0.1? capacitors. termination and input bias the in+ and in- lvds inputs are internally connectedto +1.2v through 35k (min) to provide biasing for ac- coupling (figure 1). assuming 100 interconnect, the lvds input can be terminated with a 100 resistor. match the termination to the differential impedance ofthe interconnect. use a thevenin termination, providing 1.2v bias, on an ac-coupled link in noisy environments. for intercon- nect with 100 differential impedance, pull each lvds line up to v cc with 130 and down to ground with 82 at the deserializer input (figure 10 and figure 11). thistermination provides both differential and common- mode termination. the impedance of the thevenin ter- mination should be half the differential impedance of the interconnect and provide a bias voltage of 1.2v. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 en0 en1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 bit 0 is the lsb and is deserialized first. en[1:0] are encoding bits. s[17:0] are encoded symbols. table 1. serial video phase word format 01234567891 01 11 21 31 41 51 61 71 81 9 e n 0c0c0c0c1c1c1c2c2c2c3c3c3c4c4c4c5c6c7c8 bit 0 is the lsb and is deserialized first. c[8:0] are the mapped control inputs. table 2. serial control phase word format downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer ______________________________________________________________________________________ 11 max9217 par-to-ser timing and control pll dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 v cc 130 in out 82 82 cmf rng1 rng0 max9218 ser-to-par timing and control pll dc balance/ decode 1 0 r/fouten rgb_out lock pwrdwn refclk pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 differential stp cable *caps can be at either end. ** figure 10. ac-coupled serializer and deserializer with two capacitors per link max9217 par-to-ser timing and control pll dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 v cc 130 in out 82 82 cmf rng1 rng0 max9218 ser-to-par timing and control pll dc balance/ decode 1 0 r/fouten rgb_out lock pwrdwn refclk pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 differential stp cable figure 11. ac-coupled serializer and deserializer with four capacitors per link downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 12 ______________________________________________________________________________________ input frequency detection a frequency-detection circuit detects when the lvdsinput is not switching. when not switching, all outputs except lock are low, lock is high, and pclk_out follows refclk. this condition occurs, for example, ifthe serializer is not driving the interconnect or if the interconnect is open. frequency range setting (rng[1:0]) the rng[1:0] inputs select the operating frequencyrange of the max9218 and the transition time of the out- puts. select the frequency range that includes the max9217 serializer pclk_in frequency. table 3 shows the selectable frequency ranges and the corresponding data rates and output transition times. power down driving pwrdwn low puts the outputs in high imped- ance and stops the pll. with pwrdwn 0.3v and all lvttl/lvcmos inputs 0.3v or v cc - 0.3v, the sup- ply current is reduced to less than 50?. drivingpwrdwn high initiates lock to the local reference clock (refclk) and afterwards to the serial input. lock and loss of lock ( lock ) when pwrdwn is driven high, the pll begins locking to refclk, drives lock from high impedance to high and the other outputs from high impedance to lowexcept pclk_out. pclk_out outputs refclk while the pll is locking to refclk. locking to refclk takes a maximum of 16,385 refclk cycles. when locking to refclk is complete, the serial input is moni- tored for a transition word. when a transition word is found, lock is driven low indicating valid output data, and the parallel rate clock recovered from the serialinput is output on pclk_out. pclk_out is stretched on the change from refclk to recovered clock (or vice versa). if a transition word is not detected within 2 20 cycles of pclk_out, lock is driven high and the other outputs except pclk_out are driven low. refclk is output onpclk_out and the deserializer continues monitoring the serial input for a transition word. see figure 7 for the synchronization timing diagram. output enable (outen) and busing outputs the outputs of two max9218s can be bused to form a2:1 mux with the outputs controlled by the output enable. wait 30ns between disabling one deserializer (driving outen low) and enabling the second one (dri- ving outen high) to avoid contention of the bused out- puts. outen controls all outputs. rising or falling output latch edge (r/ f ) the max9218 has a selectable rising or falling outputlatch edge through a logic setting on r/ f . driving r/ f high selects the rising output latch edge, which latchesthe parallel output data into the next chip on the rising edge of pclk_out. driving r/ f low selects the falling output latch edge, which latches the parallel outputdata into the next chip on the falling edge of pclk_out. the max9218 output-latch-edge polarity does not need to match the max9217 serializer input- latch-edge polarity. select the latch-edge polarity required by the chip being driven by the max9218. ac-coupling capacitor value vs. parallel clock frequency parallel clock frequency (mhz) capacitor value (nf) 33 30 21 24 27 35 50 65 80 95 110 125 140 20 18 36 two capacitors per link four capacitors per link rng1 rng0 parallel clock (mhz) serial data rate (mbps) output transition time 00 01 3 to 7 60 to 140 1 0 7 to 15 140 to 300 slow 1 1 15 to 35 300 to 700 fast figure 12. ac-coupling capacitor values vs. clock frequency of 18mhz to 35mhz table 3. frequency range programming downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer ______________________________________________________________________________________ 13 staggered and transition time adjusted outputs rgb_out[17:0] are grouped into three groups of six,with each group switching about 1ns apart in the video phase to reduce emi and ground bounce. cntl_out[8:0] switch during the control phase. output transition times are slower in the 3mhz-to-7mhz and 7mhz-to-15mhz ranges and faster in the 15mhz-to- 35mhz range. data enable output (de_out) the max9218 deserializes video and control data at dif-ferent times. control data is deserialized during the video blanking time. de_out high indicates that video data is being deserialized and output on rgb_out[17:0]. de_out low indicates that control data is being deserial- ized and output on cntl_out[8:0]. when outputs are not being updated, the last data received is latched on the outputs. figure 13 shows the de_out timing. power-supply circuits and bypassing there are separate on-chip power domains for digitalcircuits and lvttl/lvcmos inputs (v cc supply and gnd), outputs (v cco supply and v cco gnd), pll (v ccpll supply and v ccpll gnd), and the lvds input (v cclvds supply and v cclvds gnd). the grounds are isolated by diode connections. bypass each v cc , v cco , v ccpll , and v cclvds pin with high-frequency, surface-mount ceramic 0.1? and 0.001? capacitorsin parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. the outputs are powered from v cco , which accepts a 1.71v to 3.6v supply, allowing direct interface to inputswith 1.8v to 3.3v logic levels. cables and connectors interconnect for lvds typically has a differentialimpedance of 100 . use cables and connectors that have matched differential impedance to minimizeimpedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. board layout separate the lvttl/lvcmos outputs and lvds inputsto prevent crosstalk. a four-layer pcb with separate lay- ers for power, ground, and signals is recommended. pclk_outcntl_out de_out rgb_out = output data held pclk_out timing shown for r/f = high (rising output latch edge) control data control data video data figure 13. output timing downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer 14 ______________________________________________________________________________________ esd protection the max9218 esd tolerance is rated for the humanbody model, machine model, and iso 10605. iso 10605 specifies esd tolerance for electronic systems. the human body model discharge components are c s = 100pf and r d = 1.5k (figure 14). the iso 10605 discharge components are c s = 330pf and r d = 2k (figure 15). the machine model discharge componentsare c s = 200pf and r d = 0 (figure 16). chip information process: cmos storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m r d 1.5k c s 100pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 50 to 100 r d 2k c s 330pf figure 14. human body esd test circuit figure 15. iso 10605 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 0 c s 200pf figure 16. machine model esd test circuit. package type package code document no. 48 lqpf c48+5 21-0054 48 tqfn t4866+1 21-0141 package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . downloaded from: http:///
max9218 27-bit, 3mhz-to-35mhz dc-balanced lvds deserializer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 2/08 corrected typo (ref_in should be refclk) in figure 11 11 4 5/08 corrected lqfp package, added machine model esd, and correcteddiagrams 1, 2, 6, 7, 10, 11, 14?8 5 8/09 added automotive qualified part to ordering information 1 downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX9218ECMVTGB

	To Download MAX9218ECMVTGB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .